ISSN : 2583-2646
Effective Error Detection in VLSI Circuits Using ComparatorsM.Vinoka, Dr.S.Durairaj

This study focuses on providing simulation results and analysis of a fault-tolerant voter circuit, with a specific emphasis on the Triple Modular Redundant (TMR) system. TMR systems enhance the robustness of the voter circuit by introducing redundancy at the logic level. The proposed technique aims to minimize the area cost while ensuring multiple fault detection capability.

Physico-Chemical Analysis of Wastewater Samples Collected From the Chemistry Laboratory at Kohima Science College,
Jotsoma and Model Christian College Kohima
Vineinu Rhetso, A Chubarenla, Nikili K Zhimo, Neilanuo Huozha, Henwau Hentokhu, Daniel Kibami

Wastewater especially from the chemistry laboratory contains several toxic chemicals that are harmful to the environment although the quantity of wastewater produced by the laboratory is relatively small. This study is aimed at analyzing the physicochemical parameters of wastewater collected from the chemical laboratories in Kohima Science College Jotsoma, and Model Christian College, Kohima using standard analytical procedures.

Aerodynamic Study of Minibus in Open and Closed Window ScenariosOlusola Oloruntoba, Oluwasanmi Alonge,
Ojotu Joseph, Oluranti Abiola

Several vehicles in tropical Africa, such as Nigeria, operate with open window, and this is expected to affect aerodynamics of the vehicles. Based on established theory, Aerodynamic drag is a major component of energy losses which limit the energy available to propel a vehicle. The goal of this study is to determine the effect of open window on the aerodynamics of a typical minibus.

LDPC Decoders for the Design and Implementation of High Performance and Low Cost TechniquesSyamsuddin Millang, Siti Nuraeni

Scaling of technology and increased integration density can cause parameter and noise changes, which can increase error rates at different stages of computing. Soft failures and single-event upsets are a persistent issue in memory applications. This work is primarily concerned with the design of an effective Multi Detector/Decoder (MLDD) for fault detection and fault correction in memory applications.

Using a Kogge Stone Adder to Create Low-Area-Delay Pulsed Latches for a Shift RegisterIng. Liviu Gise

This work suggests a delay-efficient architecture for shift registers by replacing flip flops with pulsed latches. Using latches instead of flip flops is an excellent way to save space and power. Adding the required delays in pulses for latches helps mitigate the timing issue they display. Included in this is a delay-generating pulse counter. The delays can be obtained simply adding one to the counter. The proposed kogge stone architecture generates several deviations from the standard adder design while simultaneously minimizing delay to the greatest possible extent.